Photonic tensor cores
Scalable MVM engines with phase-error compensation (P-ReTiNA, MIRAGE). Targeting full-range matrix-vector multiplication on a single photonic die.
Area 01
Photonic Computing & Architecture
Designing the chip and the system that runs on light.
Philosophy
Light moves at — well — the speed of light. It doesn't dissipate heat the way electrons do when you push them through resistive wires. By using silicon photonic components — micro-ring resonators (MRRs), Mach-Zehnder interferometers (MZIs), waveguides — we can build AI accelerators that perform the matrix-vector multiplication at the core of every neural network at the speed of light, with orders-of-magnitude lower energy per operation.
But just having fast components isn't enough: the system — memory hierarchy, instruction set, dataflow — has to be rebuilt around photonics. We work at three levels simultaneously:
- Device physics. Modeling and characterizing photonic primitives under realistic non-idealities — phase error, thermal drift, fabrication variation.
- Circuit and architecture design. Composing those primitives into MVM engines, photonic tensor cores, and full accelerator pipelines.
- System-level simulation. Closing the loop between device-level tradeoffs and end-to-end neural-network accuracy, latency, and energy.
We also design the mixed-signal electronic circuits (drivers, transimpedance amplifiers, ADCs, DACs) that interface photonic cores to the rest of the system. The interface is where most photonic accelerator energy is actually spent; ignoring it makes the chip-level numbers misleading.
Open questions
- How do we tolerate process variation in photonic devices at scale?
- What's the right memory hierarchy for an analog photonic accelerator?
- Can we close the loop between photonic device design and architecture-level tradeoffs?
- How do we keep the electronic interface from dominating system energy?
Foundational reading
Where this thread started
- Shen et al., Deep learning with coherent nanophotonic circuits, Nature Photonics, 2017.
- Tait et al., Neuromorphic photonic networks using silicon photonic weight banks, Scientific Reports, 2017.
- Dang et al., BPLight-CNN: A Photonics-based Backpropagation Accelerator for Deep Learning, ACM JETC.
- Dang et al., BPhoton-CNN: A Bio-inspired Photonic CNN Accelerator, IEEE Transactions on Computers.
[Architecture diagram — pending]
Sub-themes & ongoing projects
Photonic activation functions
Building activation primitives (softmax, ReLU, sigmoid) directly in the optical domain so the entire neural network forward pass stays analog (SOFTONIC).
Mixed-signal interface circuits
Low-noise driver and TIA design, low-power ADCs / DACs — the unsung components that make photonic compute systems competitive in practice.
Variation-tolerant photonic compute
Design-for-yield strategies that absorb device-level variation without retraining the model or reworking the chip.