Memristor-FPGA neural-network acceleration
FPGA-controlled memristor crossbars as weight-storage and in-memory-MAC primitives, accessed through standard high-level synthesis tooling.
Area 04
Hybrid FPGA Integration
Bringing photonics and memristors to existing reconfigurable hardware.
Philosophy
Custom ASIC photonic chips are years away from broad adoption. Meanwhile, FPGAs are everywhere — in data centers, edge devices, embedded systems. We integrate emerging technologies — silicon photonic interconnects and non-volatile memristive memories — with FPGA platforms to build hybrid neural-network accelerators that are deployable today, with better efficiency than pure-CMOS designs.
One ongoing project pairs memristor arrays with FPGAs to run neural-network inference with non-volatile weight storage — trading off the FPGA's flexibility against the memristor's density and zero-leakage standby. Other threads explore using on-board photonic interconnects for FPGA-to-FPGA links, prototyping the system-level ideas from Area 02 in hardware.
Open questions
- How do we hide memristor write-endurance limits at the architectural level?
- What programming model fits a hybrid FPGA + memristor + photonic system?
- Where's the sweet spot between flexibility (FPGA) and efficiency (custom analog)?
- How aggressively can we age memristors before model accuracy collapses, and can training compensate?
Foundational reading
Where this thread started
- Dang et al., earlier work on aging-aware memristor training and ReRAM neural network acceleration.
- Dang et al., MEMTONIC: A Memristive-Photonic Accelerator.
- Broader literature on ReRAM in-memory computing and FPGA-based DNN accelerators (Xilinx Versal, Intel Stratix 10 NX).
[Hybrid system diagram — pending]
Sub-themes & ongoing projects
Aging-aware memristor training
Building on earlier work: training-time augmentation and online recalibration to compensate for device drift over deployment lifetime.
Photonic-FPGA hybrid prototyping
Using on-board photonic transceivers to validate at hardware speed the interconnect protocols and topologies designed in Area 02.
Programming-model design
What does a clean, FPGA-host-side API look like for a system whose accelerators are partly analog, partly photonic, partly digital?